The invention relates generally to voltage comparison circuits, and deals more particularly with a circuit which compares a differential input voltage to a predetermined voltage.
Voltage comparison circuits are well known which compare a single ended input voltage to a predetermined voltage. If the input voltage exceeds the predetermined voltage, then some appropriate action can be taken. Also, a number of such circuits with different threshold levels can be used to perform an analog to digital conversion of the input voltage. This is accomplished by using multiple comparators with different thresholds to quantize an analog signal, as in a flash A/D converter.
The simplest form of prior art comparison circuit for a singled ended input voltage comprises a high gain amplifier having one input connected to a reference voltage and the other input connected to the singled ended input voltage.
FIG. 1 illustrates another voltage comparison circuit 10 according to the prior art for comparing a single ended input voltage Vin to a predetermined voltage C2/C1.times.Vref. Circuit 10 is preferred over the simple prior art circuit described above when the circuit is implemented on an integrated circuit that has precision capacitor ratios and FET switches that require little chip area. Circuit 10 comprises an amplifier 30 and four switches or "transfer gates" S1-S4 which are formed from P or N channel MOS devices such as illustrated in U.S. Pat. 4,899,068. Switches S1 and S3 selectively pass the input voltage Vin and reference voltage Vref to precision capacitors C1 and C2, respectively. The other ends of capacitors C1 and C2 are connected together and to the inverting input of amplifier 30. Switches S2 and S4 selectively discharge the precision capacitors C1 and C2, respectively. As indicated by common switch control Phi1, switches S1 and S4 are operated in unison, and as indicated by common switch control Phi2, switches S2 and S3 are operated in unison. Thus, capacitor C1 is charged by the input voltage Vin at the same time that capacitor C2 is discharged, and capacitor C2 is charged by the reference voltage Vref at the same time that capacitor C1 is discharged. Voltage comparison circuit 10 also includes a switch Sa1 which is formed from a P or N channel MOS device and connected between the output of amplifier 30 and the inverting input. Switch control Phi1a controls switch Sa1. Amplifier 30 is capable of high gain when switch Sa1 is open (i.e open loop), for example 10,000. When switch Sa1 is closed, the output is shorted to the inverting input and amplifier 30 is configured for unity gain. The feedback path when shorted nulls any offset voltage present between the inverting and noninverting inputs of amplifier 30. A parasitic (inherent) capacitance Cp1 to ground is also illustrated.
FIG. 2 illustrates the timing provided by a state machine 35 for controlling switches S1-S4 and Sa1. At time T0, switches S1 and S4 are closed as well as switch Sa1. Thus, capacitor C1 is charged by the input voltage Vin, capacitor C2 is discharged, and any offset at the inputs to amplifier 30 is nulled. Shortly before T1, switch Sa1 is opened to cause the large gain of amplifier 30. At T1, the voltage at the noninverting input is unknown and represented by Vi, switches S1 and S4 are opened and switches S2 and S3 are closed. Because switch Sa1 was opened shortly before T1, the voltage at the inverting input is still Vi at time T1. Because the charge on capacitors C1, C2 and Cp cannot change instantaneously, the total charge Qt at the inverting input of amplifier 30 at T1 is as follows: EQU Qt1=C1(Vi-Vin)+C2.times.Vi+Cp1.times.Vi.
At time T2, the voltage at the inverting input is unknown and represented by Vf, and the total charge at the inverting input of amplifier 30 is as follows: EQU Qt2=C1.times.Vf+C2(Vf-Vref)+Cp1.times.Vf.
The total charge at the inverting input of amplifier 30 does not change from T1 to T2 due to conservation of charge. Therefore, Qt1=Qt2 and EQU C1(Vi-Vin)+C2.times.Vi+Cp1.times.Vi=C1.times.Vf+C2(Vf-Vref)+Cp1.times.Vf EQU Vf-Vi=-C1.times.Vin/Ct+C2.times.Vref/Ct EQU Ct=C1+C2+Cp1
Therefore, the output voltage Vo of amplifier 30 at T2 is as follows: EQU Vo=Av(Vf-Vi)
where Av is the open ended gain of amplifier 30. Assuming Av is large enough to saturate amplifier 30 for small differences between Vf and Vi: PA1 Vo is a logic 1 when Vin&lt;Vref.times.C2/C1 PA1 Vo is a logic 0 when Vin&gt;Vref.times.C2/C1. Consequently, circuit 10 forms a comparator for comparing the input voltage Vin to the predetermined voltage Vref.times.C2/C1. PA1 Vo is logic 1 when V1-V2&lt;Vref.times.C13/C PA1 Vo is logic 0 when V1-V2&gt;Vref.times.C13/C where C=C1=C2. While circuit 50 can perform a comparison of the difference between voltage V1 and the voltage V2 to a predetermined voltage, V1 is sampled at time T1 and V2 is sampled at time T2. If the differential voltage V1-V2 varies little from T1 to T2, then circuit 50 can provide a good comparison of the differential voltage to the predetermined voltage. However, if the differential voltage varies significantly from T1 to T2, then the difference between V1 at T1 and V2 at T2 is actually being compared to the predetermined voltage and not the instantaneous differential voltage.
FIG. 3 illustrates another prior art circuit generally designated 50 for comparing a difference between voltage V1 and voltage V2 to a predetermined voltage Vref.times.C13/C. Using the same timing as in FIG. 2, and equating the total charge at T1 to the total charge at T2 yields the following: EQU Vf-Vi=C11.times.V1/Ct+C12.times.V2/Ct+C13.times.Vref/Ct EQU Ct=C11+C12+C13+Cp10
Consequently,
Accordingly, a general object of the present invention is to provide a circuit which compares an instantaneous differential voltage to a predetermined voltage.